The invention relates to a parallel resistor circuit, an on-die termination having the same, and a semiconductor device having the on-die termination device, and more particularly, to a parallel resistor circuit which can reduce an error of a resistance value, an on-die termination having the same, and a semiconductor device having the on-die termination device.
As the operating speed of electrical products is increasing, a swing width of a signal interfaced between semiconductor devices is being gradually reduced for minimizing a delay time taken for signal transmission. However, the reduction in the swing width of the signal has a great influence on an external noise, causing the signal reflectance to become more critical at an interface terminal due to impedance mismatch. Such impedance mismatch is generally caused by an external noise, a variation of a power supply voltage, a change in an operating temperature, a change in a manufacturing process, etc. The impedance mismatch may lead to a difficulty in high-speed transmission of data and distortion of output data.
Therefore, in order to resolve the above problems, a memory device requiring high-speed performance employs an impedance matching circuit, which is called an ODT device, near around an input pad inside an IC chip. In a typical ODT scheme, source termination is performed at a transmitting end by an output circuit, and parallel termination is performed by a termination circuit connected in parallel with respect to a receiving circuit coupled to the input pad.
ZQ calibration refers to a procedure of generating calibration codes varying with process, voltage and temperature (PVT) conditions. The resistance of the ODT device, e.g., a termination resistance at a DQ pad in a memory device, is calibrated using the calibration codes resulting from the ZQ calibration. The ZQ calibration is named because the calibration is performed using a ZQ node that is a node for calibration.
FIG. 1 is a circuit diagram of a conventional calibration circuit of an ODT device.
Referring to FIG. 1, the conventional ODT device includes a calibration circuit 101 configured to perform ZQ calibration, and a termination circuit 131 configured to perform termination operation.
The calibration circuit 101 includes a first pull-up resistor unit 121, a second pull-up resistor unit 123, a pull-down resistor unit 125, a reference voltage generation unit 103, comparison units 105 and 107, a pull-up counting unit 109, and a pull-down counting unit 111, and performs ZQ calibration.
The comparison unit 105 compares a voltage of a ZQ node with a reference voltage VREF (generally set to VDDQ/2) to generate up/down signals. The voltage of the ZQ node is generated by connecting the first pull-up resistor unit 121 connected to the ZQ pad (outside a chip of the ZQ node) and a reference resistor 113 generally having the resistance of 240 Ω.
The pull-up counting unit 109 receives the up/down signals to generate pull-up calibration codes PCODE<0:N>. The pull-up calibration codes PCODE<0:N> turn on or off PMOS transistors of the first pull-up resistor unit 121 to thereby control the resistance of the first pull-up resistor unit 121. The controlled resistance of the first pull-up resistor unit 121 changes the voltage of the ZQ node again, and the comparison unit 105 compares the voltage of the ZQ node with the reference voltage VREF to output up/down signals. Through the above procedure, the first pull-up resistor unit 121 is calibrated such that a total resistance of the first pull-up resistor unit 121 is equal to the resistance of the reference resistor 113 (pull-up calibration).
The pull-up calibration codes PCODE<0:N> are input to the second pull-up resistor unit 123 to determine a total resistance of the second pull-up resistor unit 123. Here, the second pull-up resistor unit 123 has the same resistance as the first pull-up resistor unit 121 because it has the same configuration and receives the same code as the first pull-up resistor unit 121. Thereafter, a pull-down calibration is performed in a similar manner as the pull-up calibration. The pull-down calibration is performed using the comparison unit 107 and the pull-down counting unit 111 through the similar procedure to the pull-up calibration. The pull-down resistor unit 125 is calibrated such that a voltage of a node A is equal to the reference voltage VREF. That is, the pull-down resistor unit is 125 is calibrated such that the total resistance of the pull-down resistor unit 125 is equal to the total resistance of the second pull-up resistor unit 123 (pull-down calibration).
The termination circuit 131 performing the termination operation includes a pull-up termination resistor unit 141, and a pull-down termination resistor unit 143.
The pull-up and pull-down codes PCODE<0:N> and NCODE<0:N> generated by the ZQ calibration are input to pull-up and pull-down termination resistor units 141 and 143 to thereby determine the termination resistance for impedance matching. The pull-up calibration determining the resistance of the pull-up termination resistor unit 141 is performed by the pull-up calibration codes PCODE<0:N>. Likewise, the pull-down calibration determining the resistance of the pull-down termination resistor unit 143 is performed by the pull-down calibration codes NCODE<0:N>. The impedance matching with an external element can be accomplished by virtue of the resistance determined by the termination circuit 131.
Meanwhile, the ODT device does not always include both pull-up and pull-down resistor units. For example, only the pull-up resistor unit or the pull-down resistor unit may be used when the termination circuit 131 is used as an input buffer, whereas both the pull-up and pull-down resistor units should be used when the termination circuit is used as an output driver.
To be specific, as for a case where the termination circuit 131 is used as an output driver, the pull-up termination resistor unit 141 is turned on to enable a data pin DQ to ‘High’ when the termination circuit 131 outputs data ‘High’. In contrast, the pull-down termination resistor unit 143 is turned on to disable the data pin DQ to ‘Low’ when the termination circuit 131 outputs data ‘Low’.
FIGS. 2A and 2B are circuit diagrams of a conventional parallel resistor circuit.
Each of the resistor units 121, 123, 125, 141 and 143 of the ODT device of FIG. 1 includes a parallel resistor circuit illustrated in FIGS. 2A and 2B.
A plurality of parallel resistor units RSUM_0 to RSUM_14 of the parallel resistor circuit of FIG. 2A have respective resistances differing from one another, and are individually turned on or off in response to the respective pull-up calibration codes PCODE<0:N>. A total resistance of the parallel resistor circuit decreases gradually as the value N of the pull-up calibration code PCODE<0:N> increases. On the contrary, a total resistance of the parallel resistor circuit increases gradually as the value N of the pull-up calibration code PCODE<0:N> decreases. That is, when the value N of the pull-up calibration code PCODE<0:N> sequentially increases from 0 to 14, the parallel resistor units RSUM_0 to RSUM_14 are turned on sequentially from the parallel resistor unit RSUM_0 to the parallel resistor unit RSUM_14 and the resistance of the parallel resistor unit gradually decreases from the resistance of the parallel resistor unit RSUM_0 to that of the parallel resistor unit RSUM_14.
The conventional parallel resistor circuit of FIG. 2B also includes a plurality of parallel resistor units. A variation in a total resistance of the parallel resistor circuit according to the variation of pull-down calibration codes NCODE<0:N> is also identical to the resistance variation according to the variation of the pull-up calibration codes PCODE<0:N>.
A resistor with high resistance is made of a high resistivity material, and a resistor with low resistance is made of a low resistivity material. For example, the parallel resistor units RSUM_0 to RSUM_7 with high resistance may be made of a gate material with high resistivity, and the parallel resistor units RSUM_8 to RSUM_14 with low resistance may be made of a bit line material with low resistance. The resistivity means a resistance per unit area and unit length, and may vary with materials. When adopting a high resistivity material, it is possible to obtain a high resistance even using the small amount of the high resistivity material. The resistivity varies with a temperature. That is, while the resistivity of a conductor increases with an increase in a temperature, the resistivity of a semiconductor decreases with an increase in a temperature.
The resistivity of a material used for the resistor units 121, 123, 125, 141 and 143 varies due to process variations such as heat applied during fabrication of a semiconductor device, leading to a change in resistance. Therefore, a resistor made of a low resistivity material may have higher resistance than a resistor made of a high resistivity material, which is shown in FIG. 3.
FIG. 3 is a graph showing a total resistance variation of the conventional parallel resistor circuit of FIG. 2A according to pull-up calibration codes PCODE<0:N> when there are process variations.
The axis of abscissa indicates the value N of the pull-up calibration codes PCODE<0:N>, and the axis of ordinate indicates a resistance in units of ohm.
In FIG. 3, it can be observed that, due to the resistivity variation caused by process variations, the resistance of the parallel resistor unit RSUM_8 becomes higher than the resistance of the parallel resistor unit RSUM_7 although the parallel resistor unit RSUM_8 is lower in resistivity than the parallel resistor unit RSUM_7.
That is, the resistances of the conventional parallel resistor circuit included in the resistor units 121, 123, 125, 141 and 143 of the ODT device vary with process variations, and thus an error occurs during the ZQ calibration and termination operations, which makes it difficult to achieve an accurate impedance matching after all.